搜索资源列表
mul64
- 64位乘法器设计实验是我在科大的第一个课程设计，verilog程序的熟练掌握对于微电子专业的学生来讲是非常必要的，对于此次设计我也花费了很长时间。 本设计分为3个部分，即控制和（1）状态选择部分，（2）乘法器部分，（3）加法器部分。 以下我将按此顺序进行说明。需要指出的是，在实际设计中的顺序恰好是颠倒的，这与设计思路有关，在刚开始的时候由于对整体没有一个很好的把握就先选择最简单的一部分几加法器开始入手，然后就是乘法器，最后作乐一个状态控制电路将两部分联系起来。 -A 64-bit m
4-ahead_Adder
- 用Verilog HDL语言实现超前进位加法器的逻辑功能,通过ModelSim软件对4位超前进位加法器设计的仿真.-With the Verilog HDL language-ahead adder logic functions, by ModelSim software 4-ahead adder design simulation.
adder_4
- 详细介绍了四位加法器的verilog代码，还包括详细的testbench代码。-Details of the four adder verilog code, also includes detailed testbench code.
VLSI_CA1.tar
- this the implementaion of an 8-bit mirror adder in Verilog-this is the implementaion of an 8-bit mirror adder in Verilog
adder16_2
- 16位2级流水线加法器的Verilog设计-16 2 pipeline adder Verilog Design
par_addsub
- adder subtreactor verilog code
3bit_adder
- Verilog source code for a 3bit full adder build with modules using predefined nand gates.
booth4
- 4位的booth算法加法器，对计算机组成原理的学习有帮助，verilog语言编写-4-bit adder booth algorithm, the learning of computer organization help, verilog language
four_bit_addersubtractor
- Verilog code for 4 bit Adder/Subtructor
adder4
- 这是一个用verilog编写的四位加法器，编程环境是xilinx ise10.1.-This is a written with the four adder verilog, programming environment is xilinx ise10.1.
adder4
- 此源代码是基于Verilog语言的4 位全加器，4 位计数器、 4 位全加器的仿真程序、4 位计数器的仿真程序是用EDA语言描述4 位全加器，有广泛的应用。-The Verilog language source code is based on the 4-bit full adder, 4 bit counter, 4-bit full adder simulation program, 4-bit counter of the simulation program is to use la
ADD6
- 此源代码是基于Verilog语言的多种方式实现的4 选 1 MUX、多种方式实现的4 选 2 MUX 、多种方式实现的1 位半加器 、多种方式实现的1 位全加器、种方式实现的 4 位全加器 、多种方式实现的输出 UDP 元件、两个时钟信号 、选择器 和各种仿真的源代码。-This source code is based on the Verilog language, multiple ways to achieve the 4 S 1 MUX, a variety of ways to ac
Desktop
- it s a file contain Verilog code of a full adder. I hope this file is usefull for someone ! Regards !
add83coder
- 实现加法器和83译码器的功能！写的很好的verilog程序！-Adder and 83 to achieve the function of the decoder! Verilog to write a good program!
verilog_calculator
- 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
full_adder
- 用verilog在半加器的基础上实现了全加器，方法简单巧妙，对于FPGA入门学习很有帮助-In the half adder using verilog on the basis of a full adder, simple and clever, very helpful for the FPGA Starter
Simple_Verilog_Code_For_Beginner
- verilog code for beginner (adder, comparator, mux, or, and subtractor)
fpuvhdl_latest
- the code describle a floating point adder with verilog
F_ADD
- a adder with verilog-a adder with verilog
addersubtractor
- adder subtractor...this source is example to build adder and subtractor code in verilog (.v)